The present invention relates generally to testing integrated circuits and more particularly to testing the on-chip effects of noise and cross-talk on signal propagation.
Most integrated circuit (hereafter also referred to as IC devices, IC chips, or IC boards) contain a multitude of components, such as transistors, capacitors, resistors, processors, logic gates (for example AND, OR, NAND, and NOR, etc.), and memory caches, among others. These components are placed on a substrate material and connected by a series of electrical traces (i.e., conductors). Most components receive power via a power distribution bus which is connected to one or more power supplies.
Data signals are passed between components via the traces. The route used to pass a data signal between components is referred to as a data path, or logic path. The coupling of a data signal from one trace (usually called the aggressor) and another trace (usually called the victim) is referred to as cross-talk, whereas the effect of power supplies and power buses on a data signal is referred to as noise.
Today""s integrated circuits benefit from two major improvements over integrated circuits constructed a few years ago. The first improvement encompasses the integrated circuit""s operating voltage. Current integrated circuits operate at lower voltages than their predecessors. Thus, systems employing today""s integrated circuits consume less power than systems employing older integrated circuits, and as such are extremely beneficial for portable devices manufactures, for example. The second improvement encompasses component density. Current integrated circuits have higher component densities than their predecessors. In other words, current integrated circuits have more components packed within a given area than older integrated circuits. Higher density integrated circuits allow manufacturers either to offer smaller devices which perform the same functions as older devices, or to offer similar sized devices with additional functions.
Undesirable effects, however, have accompanied the shift to higher density, lower voltage integrated circuits. For example, noise and cross-talk have an increased effect on internal circuit path delays. Noise and cross-talk that would have barely been noticeable within older integrated circuits may render current integrated circuits inoperable.
Compounding the problems caused by noise and cross-talk is the lack of adequate testing methods to measure their effects on signal delays (among others) within the integrated circuit. For example, noise and cross-talk effects are usually frequency dependent. Thus, during manufacture, a chip may pass a low frequency functional test, but fail to properly function when placed and operated within a system at normal operating frequency.
Current testing methods can be grouped into two categories, simulation analysis methods and laboratory analysis methods. Both categories have limitations which impact their ability to detect conditions that may lead to integrated circuit failures.
Simulation analysis methods are said to be static-based, meaning that the amount of noise is calculated from an assumption of what is actually happening within the integrated circuit. The assumptions are based on the logic topology of the integrated circuit being tested, and are not, an actual measurement of the amount of noise found on the integrated circuit. Because assumptions must be made, simulation analysis methods are inaccurate.
Some simulation analysis methods attempt to overcome this inherent inaccuracy by employing simulation vectors to determine the effects of noise and cross-talk. However, the use of simulation vectors to accurately model a device working in a system environment consumes a great amount of time. The more complex the integrated circuit, the greater the time required for testing. Simulation analysis methods, therefore, are unlikely to be used to test today""s high density integrated circuits. Thus, the operating conditions which lead to circuit failures on today""s integrated circuits are not discovered.
Laboratory analysis methods, the second testing category, are said to be dynamic because the chip is tested as close to its normal operating frequency as possible. Laboratory analysis methods are preferable to simulation analysis methods because the xe2x80x9creal lifexe2x80x9d integrated circuit characteristics are more accurately modeled.
A laboratory testing method usually entails using high speed test equipment to supply vectors to the integrated circuit. Logic testers are then used to determine the effects of the vectors on the integrated circuit. Unfortunately, high speed test equipment is usually not capable of driving large numbers of vectors into the many signal pins present on the integrated circuit. Furthermore, the logic testers tend to operate at frequencies that are much lower than the operating frequency of the integrated circuit. Thus, even though preferable, laboratory analysis methods are usually avoided because it is difficult to drive a large integrated circuit at its system operating frequency while simultaneously gathering in-circuit measurements.
A need exists, therefore, for an apparatus and method for dynamically determining the effects of signal noise and cross-talk on on-chip signal propagation while the integrated circuit is operating in its normal mode. Furthermore, a need exists for an apparatus and method that allows the determination to be made quickly and using standard laboratory test equipment.
A method and apparatus is disclosed for dynamically testing an integrated circuit in its normal operating mode. The method and apparatus can be used to determine the effects of signal noise and cross-talk have on on-chip signal propagation. The method and apparatus allow the determination to be made quickly, using standard laboratory test equipment.
An apparatus for testing an integrated circuit is disclosed comprised of a plurality of test circuits. A first test circuit is operable to produce a signal used to determine at least one of an operating reference signal and the substrate coupling effect on components within the integrated circuit. The first test circuit has elements connected by traces and is routed to mimic a data path within the integrated circuit. A second test circuit is operable to produce a signal used to determine at least one of a cross-talk effect on the components within the integrated circuit and the accuracy of an interconnect capacitance extraction value. The second test circuit has elements connected by traces which are routed within the core logic area of the integrated circuit. A third test circuit is operable to produce a signal used to determine at least one of an effect of system noise on the operational speed of the components within the integrated circuit and a maximum degradation expected for a logic path between the components. The third test circuit has elements connected by traces. The third test circuit is randomly located within the core logic area of the integrated circuit. A fourth test circuit operable to produce a signal used to determine an effect of power supply noise on a signal propagation delay within the components within the integrated circuit. The fourth test circuit has elements connected by traces and is routed to mimic a data path within the integrated circuit. The fourth test circuit shares a power supply with the components within the integrated circuit.
The present invention encompasses a testing system having a plurality of ring oscillators constructed for dynamically measuring the effects of noise and cross-talk on the memory device. The testing system also includes a signal generator able to produce at least one of a xe2x80x98clrxe2x80x99 signal and a xe2x80x98runxe2x80x99 signal, where at least one of the xe2x80x98clrxe2x80x99 and xe2x80x98runxe2x80x99 signals are applied to at least one of the plurality of ring oscillators. The testing system also includes a signal analyzer able to retrieve an output signal from at least one of the plurality of ring oscillators.
The present invention also encompasses a method for dynamically testing the effects of signal noise and cross-talk on an integrated circuit having a core logic area. The method comprises measuring an inactive operating frequency for each of a plurality of test circuits; measuring an active operating frequency for each of a plurality of test circuits; and analyzing the plurality of inactive and active operating frequencies to determine the effects of signal noise and cross-talk on the integrated circuit.